The present invention relates to semiconductor devices and more particularly to semiconductor devices which have an electrostatic protection circuit.
With the evolution of the CMOS (Complementary Metal Oxide Semiconductor) process, constituent elements of a semiconductor integrated circuit have become more vulnerable to electrostatic discharge (ESD) and how to design the electrostatic protection circuit has become more important. A thyristor element (SCR: Silicon Controlled Rectifier) provides a high ESD protection performance per unit area and is known as an effective ESD protection element. However, for the thyristor element to demonstrate its performance potential, it is essential to design the thyristor element layout carefully.
Japanese Patent No. 4312696 describes the layout of a semiconductor device with a thyristor element as an electrostatic protection circuit as an example. In the electrostatic protection circuit described in Japanese Patent No. 4312696, two high-concentration P-type regions as thyristor element anodes are disposed in one N-type well (a thyristor element anode is hereinafter referred to as an “SCR anode”). Between the two SCR anodes, a high-concentration N-type region as a trigger TAP for connection with a trigger element is disposed. In addition, high-concentration N-type regions as thyristor element cathodes are disposed on the surfaces of P-type wells which face the two SCR anodes (a thyristor element cathode is hereinafter referred to as an “SCR cathode”).